A Content Addressable Memory (“CAM”) includes a plurality of CAM cells arranged in rows and columns. As is well-known in the art, a CAM cell can be dynamic memory based or static memory based and can be a binary cell or a ternary cell. A binary CAM cell has two possible logic states ‘1’ and ‘0’. A ternary CAM cell has three possible logic states ‘0’, ‘1’ and don't care (‘X’) encoded in two bits.
A search and compare feature allows all of the CAM cells in the CAM to be searched for an entry with data that matches a search key. An entry can include a plurality of CAM cells. For example, a 72-ternary bit entry includes 72 ternary CAM cells. If an entry matching the search key is stored in the CAM, the address of the matching entry, that is, the match address, a match flag indicating whether there is a match and a multiple match flag indicating whether there are more than one match are typically provided. The match address may be used to find data associated with the search key stored in a separate memory in a location specified by the match address.
Each entry in the CAM has an associated match line coupled to each CAM cell in the entry. Upon completion of the search, the state of the match line for the entry indicates whether the entry matches the search key. The match lines from all entries in the CAM are provided to a match line detection circuit to determine if there is a matching entry for the search key in the CAM and then the result of the match line detection circuit is provided to a priority encoder. The priority encoder selects the match entry with the highest priority if there are a plurality of match entries for the search key in the CAM. The priority encoder also provides the match address and a match flag. The match flag is enabled when there is at least one match/hit.
Typically, a CAM with a large number of CAM cells is subdivided into a plurality of banks. FIG. 1 illustrates a simplified prior art CAM 100 subdivided into a plurality of banks 102A-D, with each bank including entries comprising a plurality of CAM cells (not shown) and a supporting circuit (not shown) for the bank. Search data 104 for a search and compare operation is received at external pins of the CAM 100, routed to the center of the CAM, then routed from the center to each of the banks. The path from the external search data pin to bank 0 102a is shown as trace 106. A search for a matching entry for the search data is performed in parallel in each bank 102A-D. Upon completing a search operation for search data, each bank performs operations including priority encoding to select the match address for the highest priority matching entry stored in the respective bank. The result of the search in each bank is collected by the CAM output logic circuit 108. The CAM output logic circuit 108 is located in the center of the CAM 100. A priority encoder in the CAM output logic circuit 108 selects the highest priority matching entry from the result of the search in each bank, adds a bank identifier to the matching entry and outputs the match address 110 for the highest priority matching entry for the search word and a match flag. The operation of a priority encoder has been described but operations for other output results typically provided by a CAM such as, a match flag and a multiple match flag are also operative as known by those skilled in the art.